The present invention relates to a MOS transistor having an SOI structure, and a method of manufacturing the MOS transistor.
In accordance with recent refinement of a semiconductor device, a large scale integrated circuit (LSI) with integration of five million or more transistors has been developed. Such high integration is indispensable to increase the operation speed of a parallel processor and the like, and is more and more accelerated in accordance with increase in functions of an LSI. As the number of integrated devices is increased, however, the power consumption is also increased. Therefore, there are increasing demands for decrease in the power consumption.
The most effective technique to decrease the power consumption of an LSI is reduction of a supply voltage so as to decrease a leakage voltage. In a generation with a design rule of 0.35 xcexcm through 0.5 xcexcm, a voltage of 5 V through 3 V has been conventionally adopted, but the supply voltage is expected to be further decreased. However, since the reduction of the supply voltage degrades a driving ability of a transistor, in order to compensate the degradation of the driving ability simultaneously with pursuit of the higher operation speed, scaling of a transistor is also required.
In the scaling of a transistor, reduction of the gate length has been the most significant parameter for the higher operation speed. Additionally, as a result of the reduction of the supply voltage, scaling of a threshold voltage has also become a significant problem. The threshold voltage of a silicon MOS transistor is conventionally set at approximately 0.6 V. This voltage is comparatively small as compared with the supply voltage, and hence has been scarcely changed through generations. However, when the supply voltage is decreased to, for example, approximately 1.5 V, corresponding to a voltage of one dry battery, the proportion of the threshold voltage to the supply voltage is very large. Also, the saturation current value of a transistor is in proportion to a square of a difference between the supply voltage and the threshold voltage. In view of this, the scaling of the threshold voltage is indispensable.
The threshold voltage is a significant parameter corresponding to the subthreshold characteristic of a MOS transistor, and has strong correlation with an off-leakage current. As is shown in FIG. 13, as the threshold voltage is decreased, the off-leakage current is largely increased. This is a fatal disadvantage to portable equipment, and means that the threshold voltage cannot be simply decreased. Accordingly, there is a demand for a technique to decrease the threshold voltage for the higher operation speed without increasing the off-leakage current.
As a countermeasure against this problem, an SOI (silicon on insulator) structure is regarded to be most promising.
The SOI structure has a characteristic that spread of a depletion layer from a drain diffused layer can be suppressed by forming a buried layer out of an oxide film in a silicon substrate. Therefore, an impurity concentration of a channel region in the semiconductor substrate directly below a gate electrode can be made low, resulting in increasing the gradient of the subthreshold characteristic. For example, a normal MOS transistor has a subthreshold slope, that is, an inverse of the subthreshold characteristic, of 80 mV/dec through 90 mV/dec, whereas an SOI transistor has a subthreshold slope as small as approximately 65 mV/dec. Thus, the threshold voltage can be decreased without increasing the off-leakage current in the SOI transistor.
An SOI substrate is conventionally manufactured by, for example, a SIMOX method in which oxygen is injected into a substrate so as to directly form a buried oxide film in the substrate, a wafer bonding method in which a silicon substrate and an oxide film substrate are adhered to each other.
However, the SIMOX method has problems that the injected oxygen can remain in an upper silicon layer (SOI) and that a damage such as lattice defect can be caused in crystal by the injected oxygen. The wafer bonding method is disadvantageous in difficulty in control of the thickness of the SOI film. Also, both in the SIMOX method and the wafer bonding method, a leakage current can be caused between the source and the drain due to an interfacial level occurring on the interface between the buried oxide film and the SOI film, so that the electric characteristic of the transistor can be disadvantageously degraded.
Furthermore, in a transistor using the SOI substrate, a potential breakdown is caused between the source diffused layer and the channel region due to injected holes, so that a kink phenomenon can be easily caused. Moreover, the SOI substrate itself is disadvantageously expensive.
As described so far, there are a large number of problems in realizing an LSI including an SOI substrate.
In view of the aforementioned conventional disadvantages, the object of the invention is realizing a MOS transistor having an SOI structure without using an SOI substrate.
For the purpose of achieving this object, according to the invention, a channel lower insulating layer working as a buried oxide film is formed merely in an area below a channel region in a semiconductor substrate.
The semiconductor device of this invention comprises a semiconductor substrate including a source region and a drain region formed with a distance from each other; a gate electrode formed on the semiconductor substrate between the source region and the drain region; and a channel lower insulating layer formed below a channel region formed below the gate electrode, and in this semiconductor device, the channel lower insulating layer is formed with a distance from an isolation area disposed at both sides thereof along a gate length.
In this semiconductor device, the channel lower insulating layer formed below the channel region below the gate electrode is away from the isolation area disposed at both sides of the channel lower insulating layer along the gate length. Therefore, when a gate bias is applied, a depletion layer formed in the channel region is suppressed from spreading from the drain region, resulting in shortening time required for forming a channel in the channel region. Accordingly, an impurity concentration in the channel region can be made low, and hence, the capacitance of the depletion layer is decreased and the gradient of the subthreshold characteristic can be enlarged. As a result, the threshold voltage can be decreased without increasing the off-leakage current. Thus, low voltage drive can be realized without using an SOI substrate, and power consumption can be also decreased.
In one aspect of the semiconductor device, the channel lower insulating layer is preferably formed in a manner that the channel region is connected with an area below the channel lower insulating layer in the semiconductor substrate. In this manner, the channel lower insulating layer can be formed so as to connect the channel region with the area below the channel lower insulating layer in the semiconductor substrate. Therefore, even when an interfacial level is caused on the interface between a semiconductor layer included in the semiconductor substrate and the channel lower insulating layer, a leakage current can be prevented from flowing between the source and the drain. Furthermore, injected holes can flow to the lower portion of the semiconductor substrate, and hence, a potential breakdown is scarcely caused between the source or drain region and the channel region. Accordingly, it is possible to suppress occurrence of the kink phenomenon and the like, resulting in improving the electric characteristic of the device.
The semiconductor integrated device of this invention comprises a first semiconductor device and a second semiconductor device formed on one semiconductor substrate, and in this semiconductor integrated device, the first semiconductor device includes a first gate electrode formed on the semiconductor substrate; a first active area formed on the semiconductor substrate to be surrounded with an isolation area, the first active area including a first channel forming region with a smaller dimension along a gate width disposed below the first gate electrode, and a first source region and a first drain region extending along a gate length; and a channel lower insulating layer formed in an area below the first channel forming region with a distance from the isolation area disposed at both sides thereof along the gate length, and the second semiconductor device includes a second gate electrode formed on the semiconductor substrate; and a second active area formed on the semiconductor substrate, including a second channel forming region disposed below the second gate electrode with a larger dimension along the gate width than the first channel forming region, and a second source region and a second drain region extending along the gate length.
In this semiconductor integrated device, since the first semiconductor device includes the channel lower insulating layer formed in the area below the first channel forming region so as to be away from the isolation area disposed at both sides thereof along the gate length, time required for forming a channel in the channel region can be shortened. Therefore, an impurity concentration in the first channel forming region can be made low, and hence, the capacitance of a depletion layer can be decreased and the gradient of the subthreshold characteristic can be enlarged. Thus, the threshold voltage can be decreased without increasing the off-leakage current. In this manner, low voltage drive can be realized without using an SOI substrate. On the other hand, the second semiconductor device, formed on the same semiconductor substrate as the first semiconductor device and including the second active area, has a large drive current because its gate width is larger than that of the first semiconductor device. Furthermore, when the second semiconductor device includes, similarly to the first semiconductor device, the channel lower insulating layer below the second channel forming region with a smaller dimension along the gate width, the second semiconductor device has a different gate width from that of the first semiconductor device. Therefore, the thicknesses of the channel forming regions in these semiconductor devices are different from each other, resulting in causing a difference in the threshold voltage between the first and second semiconductor devices. Accordingly, when the first and second semiconductor devices having the different threshold voltages are combined on the same semiconductor substrate, or when the first semiconductor device applicable to low voltage drive and the second semiconductor device with a large drive current are appropriately combined on the same semiconductor substrate, the advantages of both the first and second semiconductor devices can be effectively utilized.
The method of manufacturing a semiconductor device of this invention comprises the steps of forming, on a semiconductor substrate, a mask pattern for masking an active area including a channel forming region with a smaller dimension along a gate width and a source region and a drain region extending along a gate length; forming an opening extending along the gate width in an area below the channel forming region in the semiconductor substrate by etching the semiconductor substrate with the mask pattern used, in a manner that the semiconductor substrate is largely removed toward a lower portion thereof; forming a channel lower insulating layer by filling the opening in the semiconductor substrate with an insulating film, and forming an isolation area of an insulating film around the active area; and forming a gate electrode in the channel forming region on the semiconductor substrate.
In this method of manufacturing a semiconductor device, the channel lower insulating layer is formed by filling, with the insulating film, the opening formed through etching in the area below the channel forming region below the gate electrode in the semiconductor substrate. Therefore, when a gate bias is applied, the channel lower insulating layer can suppress spread of a depletion layer formed in the channel region. As a result, time required for forming a channel in the channel region can be shortened. Accordingly, an impurity concentration in the channel forming region can be made low, and hence, the capacitance of the depletion layer can be decreased and the gradient of the subthreshold characteristic can be enlarged. Thus, the threshold voltage can be decreased without increasing the off-leakage current. In this manner, low voltage drive can be realized without using an SOI substrate, and power consumption can be also decreased.
In one aspect of the method of manufacturing a semiconductor device, the semiconductor substrate preferably has the (100) surface orientation, and wet etching is preferably adopted in etching the semiconductor substrate. In this manner, the opening extending along the gate width can be definitely formed merely in the area below the channel forming region with a smaller dimension along the gate width in the semiconductor substrate. Therefore, the channel lower insulating layer can be definitely formed merely in the area below the channel forming region.